Experienced ASIC/FPGA Design and DV Expert
Versatile engineering professional with extensive experience and expertise in all aspects of design, development, testing, and verification of ASIC/SOC. Proficient in system design and solutions. Adept at project planning and management. Strong hands-on expertise in ASIC/FPGA (application-specific integrated circuit/field-programmable gate array) production Skilled in HVL UVM, VMM, OVM, and AVM verification methodologies. Effective at troubleshooting and solving complex technical issues and problems. Collaborative team member and group leader with cross-functional teams and external stakeholders
Purvesh Khona
ASIC DESIGN AND DV EXPERT
‪(669) 222-1379‬
Email:
Address:
Fremont, CA
Phone:
EXPERIENCE
ASIC and ASIC DV Expert
As an ASIC/FPGA and ASIC DV expert, I have been responsible for SOC verification and ASIC verification. I have strong experience in UVM methodology and expertise in SystemVerilog, C++, and Verilog. My bus protocol knowledge includes PCIe, PCI, DDR, QDR, AHB and I have processor experience with RISC-V, ARM, PowerPC.
I have been responsible for design of memory controllers and accelerators for Sun Microsystems's network storage products
My experience involves, design, DV and technical leadership of engineering teams with varied experience levels.
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I have served industry as a full time employee as well as highly skilled consultant over the years.
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Nov 2021 to Jan 2023
Amazon Inc.
L6 Senior Verification Engineer
As member of Kuper team, updated validation systems and refactored complex code for TX engine.
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Produced self-contained UVC for IP block that was repeated throughout chip to prepare for future projects.
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Designed UVC for SOC-level integration capable of identifying integration issues in addition to block-level validation of the IP.
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Produced complex vector-oriented test environment that processed large number of text files, generated vectors based on algorithms, and verified the result for customer terminal and gateway chips.
June 2020 to Nov 2021
Meta (Facebook)
Senior Verification Consultant
Designed and constructed a new unit-level test environment for a block in graphics pipeline chipset developed for Facebook.
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Significantly reduced and streamlined development time and met goals by designing constrained random framework that is configured by knobs and scalable from block to chip
October 2018 to June 2020
Samsung Semiconductor
Senior Verification Engineer
Created verification system for new SOC architecture for new RFIC chipset with platform team at leading technology manufacturer. Conceived, built and executed a full random UVM environment to test RFIC chipset.
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Devised a unique testing flow to enable chip and to send traffic via text files with a small parser to apply high- level constructs. Engineers on FW /RTL Sims and Post Silicon Validation team extensively used the process.
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Streamlined process by enabling cross-functional teams to be decoupled from the requirement for support from verification engineer.
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Created randsequence based- flow to validate SOC that generated complex bus transactions. Within one day of deployment, the environment identified a Silicon lab bug which had not been found previously.
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Designed and employed a .txt file driven vector-based testing flow. Built small txt parser to facilitate high-level constructs to assist FW/RTL Sims and Post Silicon Validation team.
Senior Verification Consultant
Developed new test sequences, upgraded UVM environment, and ran running gate-level sims to support verification of RFIC SOC chips for Samsung’s 5G solution. Managed multiple chipsets simultaneously.
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Taped out multiple chips.
January 2018 to October 2018
Western Digital
Senior Verification Consultant
Provided technical support for enterprise flash-storage chip.
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Developed sequences at SOC level and verified sub-blocks.​
Other Previous Experience
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Samsung/Consultant: Streamlined development time. Improved and verified CCV (culling, clipping, viewport) fixed-function (OpenGL) graphics block. Set up environment to manage vectors, and constrained random flow using randsequences.
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San Disc/Verification Consultant: Oversaw C-based testing and verification of ARM R-5 based SOC. Identified and solved architectural issues. Leveraged full arm simulation tool chain to build, analyze, and maintain bootfile, scatter files and tarmac files.
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Sun Microsystems/Lead Design Engineer: Led 7-member cross-functional team that developed all network storage ASICs and FPGAs on multiple product families. Managed design, coding, FPGA implementation, and verification for RAID memory controller ASICs and Fibre channel protocol engines. Received multiple outstanding achievement awards from VPs of Engineering and Operations.
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Cisco Systems/Senior Verification Consultant: Managed and refactored complex port info manager component that multiple teams were using. Created custom factory pattern using SV code so that development is decoupled from team to team
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Cisco Systems/Senior Verification Engineer: Architected and built verification system and test plan for complex 400,000 raw logic gate-count block of memory controller for a complex ASIC with multiple acceleration engines. Wrapped VMM library with proprietary CPP library. Member of 5-member team that created advanced CPP library.
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AMCC/Lead Design Engineer: Led 14-member team in US and Romania that verified 2 chips, with accountability for project infrastructure, planning, and execution. Produced SOC oriented on AHB bus and PPC (with AHB bridge). Served as liaison with customer (Panasonic) for progress briefings.
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D.E.Shaw Research : Was part of niche ASIC team as consultant to develop super computer. Was responsible for bringing up Gen3 PCIe x 16 link. Gen3 spec was still not full developed, we were second company at that time to use Gen3 PCIE.
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Iron Key: Was part of ASIC development team as consultant to help them validate the secure USB pen drive chip
EDUCATION
MUMBAI(BOMBAY) UNIVERSITY
Bachelor's in Electronics Engineering
As part of my Bachelor's degree in Electrical Engineering, I studied advanced topics in ASIC design and verification.
SOME CONSULTING CLIENTS
SKILLS
ASIC Verification - Expert
SystemVerilog - Expert
C++ - Sound Knowledge
UVM - Expert
Verilog - Expert
PCIe - Extensive work experience
AHB - Sound Knowledge
UVM ENVIROMENT ARCHITECT - Expert
EXPERTISE
SOC Verification
Expert in hardware/software co-verification. Have experience with bootcode development, C / SV based verification, BFM based SOC verification, Instruction set simulator based SOC verification
ASIC Verification
Expert in block to chip verification. Building complex environments using systemverilog, using SV and UVM or VMM
Languages & Environments
System Verilog, UVM, Verilog, PERL, JAVA, Vaadin (Java based UI framework), C, C++
Processes
Circuit board design, Chip development, FPGA designs, Conversion of FPGAs to ASICs/Structured ASICs, Porting of large ASICs/SOCs to FPGAs on a custom or prebuilt board, Building large block to CHIP UVM environments, Co-simulation using C and HVLs
Protocols
PCI, PCI-X, PCIEe, Infiniband, AMBA AHB, SDRAM, DDR, QDR, PPC based SOC designs, PLB bus
Tools
VCS, Questa, Verdi, Git, Perforce, Xilinx FPGAs, Altera FPGAs, Lightspeed Structured ASICs, LSI gate arrays, PowerPC instruction set simulators for co-simulation